Unified Coverage Report :: Module

Module : dti_soffqbcka01

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00			50.00

Source File(s) :
/nfs_project/gemini/DV/mahmood/ddr_main_new/gemini/design/ip/dti/libs/dti_tm28hpcp_ddr4_phy/hdl/library/dti_tm28hpcp_l30_stdcells_10t_rev1p0p3.v

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst35.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst60.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst73.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst76.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst79.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst96.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst103.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst132.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst150.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst152.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst153.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst169.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst170.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst190.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst194.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst195.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst197.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst228.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst231.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst241.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst242.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst247.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst260.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst292.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst297.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst317.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst323.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst331.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst336.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst354.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst374.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst375.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst385.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst387.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst399.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst413.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst430.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst433.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst440.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst448.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst462.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst467.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst492.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst515.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst516.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst524.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst536.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst579.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst582.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst602.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst607.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst611.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst621.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst627.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst629.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst637.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst647.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst662.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst677.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst682.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst683.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst686.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst694.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst700.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst709.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst719.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst721.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst734.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst749.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst760.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst761.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst792.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst811.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst814.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst817.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst821.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst822.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst838.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst849.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst877.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst904.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst921.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst933.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst935.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst951.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst982.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst991.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst996.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst997.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1001.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1013.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1029.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1034.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1073.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1076.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1083.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1120.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1123.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1128.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1136.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1150.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1168.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1175.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1185.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1194.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1200.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1213.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1217.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1218.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1229.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1231.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1246.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1247.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1250.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1258.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1276.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1294.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1343.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1347.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1350.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1354.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1364.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1415.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1424.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1431.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1438.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1456.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1458.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1461.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1469.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1551.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1592.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1597.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1629.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1643.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1659.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1668.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1672.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1683.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1700.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1702.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1713.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1723.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1725.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1726.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1746.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1747.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1750.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1755.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1756.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1776.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1785.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1805.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1807.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1808.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1832.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1839.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1841.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1842.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1851.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1859.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1891.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1900.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1905.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1910.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1911.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1933.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1937.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1944.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1949.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1970.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2012.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2014.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2037.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2050.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2065.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2069.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2074.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2093.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2096.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2101.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2102.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2104.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2108.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2112.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2113.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2117.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2131.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2137.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2138.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2148.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2163.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2183.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2206.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2208.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2224.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2240.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2243.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2249.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2258.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2275.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2279.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2319.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2321.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2340.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2345.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2371.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2377.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2378.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2386.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2397.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2400.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2402.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2404.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2419.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2421.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2453.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2454.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2460.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2471.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2486.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2517.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2521.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2526.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2537.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2547.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2553.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2555.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2612.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2623.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2642.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2683.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2689.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2700.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2718.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2736.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2739.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2745.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2761.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2777.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2781.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2789.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2790.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2795.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2825.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2846.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2863.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2868.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2874.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2876.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2877.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2882.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2884.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2898.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2914.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2917.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2918.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2924.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2929.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2935.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2941.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2964.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2970.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2971.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2987.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2992.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2995.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3012.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3022.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3025.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3030.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3031.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3036.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3043.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3045.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3051.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3057.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3071.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3082.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3111.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3112.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3118.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3175.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3192.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3197.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3222.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3227.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3235.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3241.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3242.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3254.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3259.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3267.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3272.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3282.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3299.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3321.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3337.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3343.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3347.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3353.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3371.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3375.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3382.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3400.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3410.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3414.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3430.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3457.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3473.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3505.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3550.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3555.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3586.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3604.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3612.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3620.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3630.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3632.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3636.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3657.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3660.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3663.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3666.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3695.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3748.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3753.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3770.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3793.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3801.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3805.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3815.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3821.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3830.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3840.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3846.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3857.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3876.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3905.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3906.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3948.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3950.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3979.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3986.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4000.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4002.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4013.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4024.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4041.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4044.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4051.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4057.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4066.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4067.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4069.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4110.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4122.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4125.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4127.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4131.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4134.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4148.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4177.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4181.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4193.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4201.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4215.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4220.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4222.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4230.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4235.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4240.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4249.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4313.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4327.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4349.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4353.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4369.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4385.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4391.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4399.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4414.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4427.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4430.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4434.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4446.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4450.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4481.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4521.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4524.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4525.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4549.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4556.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4578.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4593.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4601.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4604.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4605.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4607.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4616.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4619.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4657.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4662.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4673.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4677.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4682.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4702.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4734.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4735.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4747.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4750.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4751.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4757.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4765.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4787.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4789.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4818.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4835.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4837.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4859.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4872.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4887.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4893.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4924.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4936.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4939.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4949.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5015.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5046.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5058.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5079.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5089.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5109.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5117.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5124.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5131.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5134.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5146.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5155.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5156.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5171.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5179.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5192.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5197.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5198.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5206.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5212.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5223.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5230.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5235.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5238.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5243.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5256.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5259.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5276.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5291.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5299.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5305.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5327.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5337.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5341.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5343.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5358.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5360.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5379.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5389.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5436.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5443.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5445.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5452.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5466.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5479.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5483.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5487.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5498.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5531.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5543.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5547.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5598.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5617.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5623.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5624.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5637.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5640.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5671.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5672.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5683.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5691.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5693.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5701.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5709.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5713.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5741.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5791.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5799.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5802.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5808.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5817.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5823.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5834.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5843.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5867.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5904.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5925.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5926.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5933.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5935.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5958.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5968.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5970.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5974.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5995.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6001.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6025.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6034.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6035.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6039.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6040.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6054.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6072.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6088.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6095.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6109.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6110.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6112.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6117.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6119.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6126.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6133.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6135.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6162.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6164.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6165.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6174.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6176.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6180.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6197.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6233.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6283.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6301.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6306.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6313.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6336.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6378.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6406.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6407.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6436.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6450.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6460.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6468.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6483.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6492.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6512.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6513.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6515.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6541.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6554.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6580.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6581.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6617.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6666.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6675.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6688.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6701.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6712.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6717.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6727.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6734.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6743.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6745.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6759.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6762.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6774.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6785.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6798.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6811.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6825.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6836.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6837.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6842.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6860.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6875.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6888.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6889.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6901.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6918.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6925.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6928.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6940.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6946.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6961.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6973.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6974.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6993.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7021.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7024.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7052.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7059.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7064.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7092.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7093.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7155.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7157.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7176.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7180.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7191.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7195.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7196.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7233.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7235.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7241.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7243.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7249.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7254.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7259.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7289.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7294.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7297.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7330.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7343.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7349.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7351.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7357.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7395.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7402.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7405.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7423.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7431.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7433.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7442.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7452.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7464.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7494.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7512.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7541.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7572.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7623.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7626.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7636.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7678.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7682.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7683.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7692.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7727.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7738.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7763.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7773.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7776.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7782.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7787.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7788.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7789.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7791.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7829.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7831.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7834.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7842.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7859.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7878.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7908.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7917.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7935.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7946.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7949.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7971.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7982.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7996.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8005.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8010.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8013.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8025.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8030.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8031.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8041.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8048.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8066.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8070.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8072.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8076.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8078.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8093.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8105.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8110.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8118.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8184.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8186.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8193.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8204.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8207.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8219.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8225.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8231.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8261.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8301.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8334.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8354.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8393.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8409.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8433.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8438.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8442.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8451.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8481.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8487.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8493.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8504.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8519.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8521.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8543.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8572.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8574.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8629.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8634.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8638.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8645.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8662.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8667.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8702.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8724.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8728.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8750.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8753.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8763.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8771.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8780.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8807.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8810.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8811.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8825.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8850.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8851.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8861.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8878.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8899.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8906.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8911.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8923.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8935.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8946.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8956.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8963.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8990.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9001.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9007.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9033.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9054.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9082.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9091.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9093.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9110.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9120.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9132.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9160.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9167.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9168.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9171.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9178.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9183.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9185.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9190.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9192.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9217.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9236.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9241.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9243.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9244.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9264.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9297.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9302.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9313.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9335.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9356.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9357.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9360.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9378.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9420.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9427.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9431.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9447.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9448.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9471.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9481.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9485.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9493.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9526.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9536.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9549.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9567.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9576.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9578.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9583.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9587.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9588.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9596.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9626.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9647.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9649.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9680.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9682.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9683.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9686.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9709.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9713.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9714.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9725.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9731.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9735.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9760.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9767.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9779.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9781.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9782.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9791.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9801.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9803.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9849.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9861.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9868.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9878.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9882.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9884.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9885.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9903.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9919.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9927.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9930.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9955.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9957.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9999.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10007.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10008.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10012.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10013.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10019.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10036.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10053.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10076.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10095.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10141.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10145.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10150.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10174.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10179.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10181.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10208.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10220.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10226.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10235.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10259.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10276.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10281.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10294.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10297.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10307.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10308.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10312.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10336.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10339.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10342.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10344.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10351.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10365.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10390.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10396.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10413.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10429.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10447.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10460.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10461.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10463.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10471.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10483.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10492.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10505.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10509.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10510.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10512.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10538.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10545.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10554.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10571.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10576.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10582.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10596.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10611.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10613.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10614.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10621.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10622.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10647.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10659.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10663.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10682.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10699.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10719.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10733.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10779.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10782.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10788.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10801.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10817.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10820.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10860.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10862.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10871.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10874.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10875.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10876.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10877.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10890.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10906.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10924.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10929.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10932.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10946.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10948.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10953.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10965.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10982.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10992.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11008.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11029.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11032.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11042.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11045.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11057.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11063.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11065.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11073.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11081.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11090.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11119.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11122.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11151.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11174.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11194.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11195.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11249.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11269.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11277.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11281.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11335.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11337.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11346.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11370.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11380.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11391.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11414.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11416.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11417.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11429.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11448.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11454.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11455.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11479.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11507.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11524.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11528.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11533.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11548.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11577.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11609.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11612.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11619.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11624.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11626.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11627.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11679.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11694.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11711.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11714.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11729.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11754.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11765.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11784.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11800.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11805.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11823.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11864.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11871.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11896.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11915.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11932.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11948.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11982.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11994.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11998.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12002.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12020.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12043.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12056.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12071.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12082.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12086.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12087.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12093.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12094.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12097.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12116.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12128.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12132.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12146.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12148.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12163.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12169.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12207.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12244.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12255.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12289.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12299.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12303.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12312.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12353.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12365.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12372.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12385.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12402.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12408.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12416.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12419.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12422.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12434.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12438.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12460.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12463.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12466.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12486.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12488.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12518.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12520.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12530.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12553.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12577.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12594.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12616.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12654.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12660.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12665.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12671.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12679.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12688.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12690.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12718.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12728.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12729.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12743.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12746.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12782.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12784.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12788.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12791.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12802.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12803.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12810.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12818.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12822.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12825.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12827.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12832.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12842.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12846.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12890.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12908.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12914.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12919.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12925.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12944.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12952.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12954.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12966.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12967.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12992.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12995.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12998.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13011.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13032.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13041.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13070.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13085.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13094.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13096.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13106.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13155.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13163.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13171.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13182.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13227.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13243.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13271.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13273.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13278.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13283.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13296.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13306.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13320.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13362.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13397.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13413.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13437.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13441.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13462.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13509.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13540.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13544.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13560.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13586.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13595.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13609.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13612.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13623.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13647.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13652.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13659.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13669.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13671.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13674.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13678.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13689.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13693.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13705.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13721.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13729.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13732.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13745.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13753.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13767.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13769.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13791.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13836.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13837.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13856.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13896.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13928.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13933.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13935.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13954.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13990.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14002.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14007.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14032.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14046.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14048.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14064.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14076.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14078.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14083.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14108.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14145.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14154.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14163.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14190.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14215.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14231.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14238.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14240.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14257.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14260.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14318.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14349.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14370.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14385.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14410.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14413.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14434.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14444.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14455.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14460.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14491.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14517.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14526.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14532.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14538.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14543.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14560.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14562.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14581.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14583.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14611.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14624.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14627.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14629.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14633.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14647.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14649.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14653.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14667.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14692.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14693.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14698.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14702.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14704.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14727.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14732.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14766.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14773.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14784.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14792.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14796.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14827.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14865.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14873.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14878.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14886.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14934.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14940.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14952.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14982.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14991.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15005.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15052.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15062.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15064.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15065.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15073.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15085.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15110.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15111.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15122.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15133.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15135.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15145.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15179.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15201.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15206.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15210.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15216.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15238.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15271.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15276.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15285.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15294.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15320.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15368.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15376.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15381.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15393.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15421.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15432.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15457.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15460.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15468.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15472.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15498.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15499.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15508.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15516.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15523.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15526.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15534.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15540.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15567.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15580.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15584.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15588.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15593.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15601.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15603.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15612.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15634.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15662.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15691.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15726.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15737.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15746.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15750.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15766.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15767.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15773.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15774.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15782.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15787.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15793.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15796.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15805.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15808.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15814.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15845.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15863.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15864.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15868.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15875.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15903.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15916.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15928.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15953.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15956.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15961.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16062.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16074.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16090.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16099.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16103.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16105.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16110.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16143.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16171.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16186.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16202.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16205.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16209.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16230.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16261.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16271.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16273.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16286.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16293.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16295.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16302.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16317.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16318.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16346.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16353.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16384.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16386.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16387.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16405.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16415.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16433.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16435.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16442.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16462.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16483.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16485.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16506.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16516.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16524.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16526.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16527.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16533.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16545.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16557.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16575.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16587.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16601.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16606.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16622.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16629.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16667.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16708.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16718.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16736.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16737.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16791.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16803.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16805.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16814.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16829.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16834.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16873.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16883.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16888.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16916.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16917.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16937.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16945.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16948.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16964.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16979.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16982.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16990.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17000.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17001.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17008.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17011.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17024.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17035.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17036.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17041.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17047.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17057.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17070.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17100.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17109.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17148.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17152.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17191.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17201.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17203.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17218.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17220.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17237.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17281.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17287.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17294.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17299.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17309.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17348.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17349.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17355.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17375.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17381.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17390.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17416.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17456.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17466.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17469.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17473.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17487.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17503.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17504.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17509.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17514.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17515.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17533.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17554.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17569.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17593.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17602.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17606.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17612.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17617.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17622.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17626.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17643.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17662.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17669.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17677.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17692.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17693.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17704.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17734.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17741.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17774.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17782.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17819.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17824.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17835.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17841.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17851.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17884.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17894.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17910.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17924.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17953.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17957.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17966.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17970.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17981.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17985.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17999.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18031.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18032.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18034.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18036.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18038.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18041.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18071.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18087.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18089.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18094.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18105.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18106.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18130.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18132.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18143.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18183.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18191.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18222.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18232.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18254.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18257.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18268.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18280.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18307.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18331.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18350.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18357.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18405.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18408.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18425.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18426.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18447.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18451.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18452.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18455.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18522.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18527.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18530.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18544.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18551.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18554.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18557.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18585.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18624.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18652.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18671.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18674.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18688.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18708.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18723.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18755.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18758.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18778.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18809.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18811.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18815.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18838.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18847.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18877.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18895.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18903.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18921.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18937.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18951.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18973.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18991.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19025.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19026.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19035.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19039.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19042.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19048.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19059.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19060.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19068.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19083.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19091.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19098.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19109.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19128.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19129.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19134.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19138.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19153.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19156.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19176.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19182.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19185.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19190.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19217.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19225.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19254.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19256.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19271.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19274.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19286.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19310.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19353.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19366.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19378.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19389.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19404.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19406.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19414.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19419.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19437.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19468.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19498.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19499.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19513.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19534.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19543.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19552.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19567.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19575.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19603.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19609.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19619.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19631.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19636.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19638.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19674.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19681.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19682.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19701.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19711.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19717.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19722.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19727.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19745.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19746.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19747.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19760.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19765.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19772.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19777.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19792.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19796.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19813.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19819.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19824.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19857.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19881.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19891.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19903.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19904.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19928.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19957.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19965.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19972.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19990.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19995.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20005.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20008.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20010.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20012.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20020.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20021.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20024.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20034.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20037.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20076.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20097.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20103.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20109.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20111.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20112.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20121.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20132.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20140.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20151.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20153.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20175.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20176.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20200.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20201.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20206.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20212.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20213.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20217.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20239.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20273.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20279.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20285.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20286.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20298.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20303.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20323.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20349.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20362.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20384.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20432.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20441.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20444.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20448.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20449.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20456.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20469.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20470.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20514.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20536.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20551.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20572.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20574.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20594.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20601.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20628.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20642.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20685.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20692.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20707.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20716.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20718.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20765.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20771.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20785.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20809.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20815.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20895.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20898.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20903.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20918.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20943.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20968.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20980.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21019.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21028.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21040.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21043.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21045.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21048.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21050.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21056.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21066.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21080.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21113.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21129.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21131.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21132.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21165.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21166.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21171.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21191.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21237.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21241.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21244.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21279.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21313.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21315.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21320.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21321.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21353.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21360.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21364.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21380.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21386.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21389.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21393.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21403.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21443.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21454.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21479.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21484.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21535.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21547.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21550.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21562.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21582.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21584.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21593.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21597.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21609.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21610.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21620.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21630.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21636.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21637.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21661.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21671.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21689.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21738.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21749.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21774.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21781.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21783.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21809.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21810.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21819.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21820.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21834.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21860.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21872.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21878.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21879.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21892.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21895.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21913.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21919.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21956.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21961.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21979.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21988.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21998.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22002.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22036.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22063.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22071.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22078.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22082.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22087.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22091.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22120.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22140.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22141.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22153.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22165.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22167.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22232.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22278.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22279.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22282.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22285.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22315.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22380.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22405.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22407.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22422.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22424.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22428.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22439.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22457.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22477.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22488.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22489.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22491.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22512.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22532.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22535.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22591.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22631.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22633.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22640.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22672.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22700.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22703.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22707.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22731.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22733.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22735.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22740.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22743.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22753.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22769.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22771.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22774.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22800.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22811.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22817.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22819.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22837.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22838.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22847.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22850.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22863.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22871.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22872.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22884.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22889.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22900.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22936.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22940.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22947.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22956.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22962.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22976.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22980.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22984.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22985.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23001.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23014.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23040.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23047.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23054.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23061.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23062.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23076.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23092.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23097.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23098.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23102.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23123.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23147.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23159.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23165.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23180.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23201.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23218.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23275.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23283.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23289.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23296.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23305.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23310.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23312.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23322.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23335.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23346.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23357.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23367.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23368.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23379.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23410.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23420.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23455.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23460.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23464.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23476.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23477.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23486.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23527.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23568.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23572.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23574.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23641.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23642.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23643.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23673.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23675.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23705.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23711.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23729.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23736.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23739.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23751.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23760.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23761.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23779.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23787.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23789.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23819.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23847.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23849.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23856.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23863.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23876.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23891.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23902.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23904.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23922.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23934.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23937.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23963.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23967.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23979.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24009.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24016.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24025.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24029.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24046.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24049.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24089.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24110.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24129.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24133.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24148.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24155.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24166.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24189.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24196.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24200.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24206.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24212.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24215.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24239.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24247.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24253.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24270.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24276.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24292.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24313.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24338.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24352.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24354.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24364.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24371.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24387.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24390.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24399.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24418.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24440.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24441.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24450.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24465.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24473.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24475.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24489.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24500.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24509.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24511.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24564.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24604.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24611.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24626.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24645.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24648.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24683.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24685.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24692.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24694.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24699.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24706.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24709.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24712.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24739.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24748.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24765.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24768.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24776.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24797.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24803.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24828.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24839.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24842.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24845.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24848.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24855.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24862.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24874.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24937.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24973.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25010.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25019.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25021.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25024.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25042.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25059.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25062.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25065.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25087.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25093.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25133.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25137.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25140.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25141.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25150.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25170.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25172.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25181.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25186.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25196.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25206.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25248.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25260.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25267.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25295.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25296.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25299.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25301.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25311.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25318.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25319.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25324.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25389.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25401.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25448.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25456.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25457.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25469.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25496.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25497.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25512.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25515.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25517.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25537.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25541.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25548.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25560.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25575.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25578.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25581.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25587.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25591.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25598.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25631.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25657.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25676.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25692.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25710.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25712.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25763.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25781.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25797.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25799.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25804.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25805.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25813.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25814.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25824.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25833.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25834.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25836.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25855.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25872.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25882.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25891.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25910.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25923.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25940.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26012.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26027.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26042.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26071.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26076.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26082.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26101.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26116.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26136.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26142.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26145.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26149.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26152.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26153.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26188.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26204.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26208.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26220.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26234.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26274.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26280.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26288.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26291.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26296.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26310.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26319.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26328.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26331.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26353.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26370.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26381.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26398.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26404.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26408.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26416.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26418.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26424.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26440.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26459.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26475.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26514.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26531.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26541.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26545.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26548.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26549.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26553.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26559.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26567.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26588.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26589.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26592.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26603.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26604.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26610.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26619.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26640.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26641.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26668.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26676.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26705.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26713.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26714.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26737.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26741.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26748.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26765.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26770.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26780.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26789.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26836.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26862.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26900.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26905.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26918.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26920.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26924.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26931.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26932.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26939.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26945.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26956.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26967.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26978.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26986.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26991.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26998.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27020.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27030.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27040.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27062.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27086.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27098.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27103.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27115.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27129.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27138.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27142.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27154.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27176.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27184.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27189.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27230.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27238.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27247.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27274.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27289.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27295.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27304.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27356.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27369.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27372.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27374.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27390.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27417.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27422.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27423.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27432.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27437.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27461.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27468.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27475.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27478.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27479.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27489.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27490.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27499.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27511.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27532.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27541.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27550.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27562.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27572.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27574.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27658.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27661.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27687.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27688.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27699.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27704.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27715.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27716.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27748.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27758.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27760.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27761.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27782.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27823.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27824.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27827.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27863.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27873.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27878.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27890.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27895.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27919.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27935.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27954.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27956.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27963.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27977.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27981.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27988.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28012.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28043.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28050.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28056.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28058.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28061.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28064.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28073.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28084.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28091.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28103.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28108.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28115.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28121.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28153.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28156.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28186.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28187.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28203.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28206.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28228.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28242.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28252.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28262.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28263.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28280.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28331.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28339.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28343.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28353.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28381.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28384.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28390.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28410.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28434.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28439.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28450.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28476.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28497.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28510.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28547.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28578.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28583.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28616.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28625.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28644.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28666.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28685.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28692.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28702.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28734.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28737.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28740.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28749.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28755.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28781.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28800.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28818.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28822.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28833.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28838.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28850.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28853.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28862.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28867.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28905.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28912.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28933.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28959.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29021.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29050.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29064.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29105.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29116.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29130.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29160.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29170.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29173.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29174.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29230.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29232.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29243.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29246.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29248.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29283.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29299.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29326.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29346.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29355.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29369.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29398.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29440.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29446.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29473.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29476.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29550.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29558.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29581.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29588.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29591.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29617.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29625.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29705.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29722.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29723.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29724.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29725.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29787.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29797.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29801.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29820.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29858.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29873.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29881.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29896.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29900.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29914.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29921.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29938.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29943.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29964.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29966.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29969.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29973.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29995.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30034.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30044.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30058.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30064.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30083.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30097.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30098.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30111.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30125.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30140.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30164.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30185.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30195.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30228.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30261.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30274.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30287.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30291.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30310.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30319.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30320.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30338.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30386.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30406.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30425.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30443.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30447.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30458.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30461.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30463.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30470.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30476.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30481.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30492.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30493.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30504.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30507.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30521.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30531.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30549.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30563.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30565.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30567.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30577.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30583.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30584.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30588.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30604.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30613.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30615.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30634.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30637.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30638.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30666.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30673.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30680.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30688.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30689.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30697.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30745.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30754.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30759.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30760.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30764.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30773.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30779.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30795.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30797.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30818.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30853.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30859.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30877.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30887.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30903.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30922.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30929.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30938.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30968.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30974.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30981.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30996.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31007.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31031.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31037.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31040.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31042.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31051.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31063.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31065.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31071.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31072.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31086.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31092.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31108.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31121.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31136.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31148.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31161.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31162.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31164.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31170.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31176.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31180.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31182.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31191.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31193.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31237.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31240.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31263.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31287.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31291.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31293.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31306.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31326.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31451.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31481.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31484.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31488.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31517.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31520.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31530.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31539.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31558.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31570.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31576.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31585.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31591.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31629.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31652.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31683.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31695.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31708.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31727.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31730.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31736.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31740.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31747.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31758.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31788.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31811.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31815.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31827.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31831.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31841.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31846.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31855.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31856.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31863.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31871.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31895.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31921.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31944.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31964.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31973.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31976.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31983.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31986.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31987.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32008.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32023.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32027.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32034.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32047.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32051.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32052.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32055.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32057.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32066.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32070.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32076.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32083.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32088.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32103.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32124.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32135.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32140.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32141.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32142.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32161.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32182.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32189.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32192.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32247.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32253.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32255.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32265.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32304.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32311.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32323.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32348.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32363.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32373.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32376.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32386.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32395.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32429.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32435.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32447.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32459.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32509.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32520.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32521.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32535.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32551.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32587.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32589.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32628.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32641.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32660.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32678.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32712.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32717.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32725.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32728.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32730.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32740.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32761.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32764.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32776.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32793.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32846.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32900.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32902.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32925.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32930.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32931.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32945.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32948.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32951.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32964.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32967.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32983.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32991.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33007.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33011.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33030.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33058.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33072.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33075.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33099.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33108.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33116.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33118.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33140.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33182.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33220.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33235.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33239.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33241.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33243.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33249.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33252.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33262.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33277.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33291.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33300.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33313.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33319.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33337.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33343.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33376.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33377.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33412.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33424.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33430.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33434.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33435.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33452.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33461.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33470.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33473.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33480.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33482.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33485.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33493.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33518.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33520.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33534.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33535.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33560.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33581.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33592.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33598.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33602.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33613.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33615.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33628.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33640.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33642.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33647.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33657.xdti_28hc_10t_30_soffqbcka01	0.00			0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33664.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33667.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33672.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33678.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33701.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33716.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33721.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33723.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33740.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33747.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33756.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33791.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33797.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33799.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33806.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33814.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33823.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33831.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33843.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33848.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33854.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33858.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33880.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33889.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33892.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33919.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33921.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33926.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33949.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33981.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33988.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33989.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33992.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33994.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33997.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34035.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34067.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34071.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34083.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34092.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34099.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34102.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34108.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34115.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34138.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34139.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34165.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst13.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst17.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst19.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst33.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst46.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst80.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst86.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst92.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst109.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst117.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst123.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst144.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst160.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst191.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst210.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst251.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst264.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst265.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst271.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst278.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst281.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst306.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst310.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst342.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst349.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst362.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst430.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst435.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst465.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst466.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst477.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst489.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst491.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst518.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst531.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst551.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst569.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst582.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst597.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst611.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst655.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst667.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst678.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst730.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst734.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst754.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst757.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst770.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst788.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst822.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst830.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst855.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst919.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst936.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst941.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst948.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst967.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst969.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst975.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst999.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1032.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1056.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1058.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1069.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1078.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1108.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1134.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1139.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1153.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1157.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1197.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1215.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1218.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1225.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1228.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1255.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1258.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1284.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1286.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1295.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1311.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1314.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1326.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1344.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1363.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1369.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1377.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1383.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1387.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1410.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1460.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1466.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1479.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1484.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1485.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1490.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1491.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1541.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1553.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1589.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1612.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1652.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1656.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1673.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1676.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1679.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1686.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1718.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1742.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1745.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1748.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1759.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1760.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1776.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1788.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1811.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1853.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1861.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1863.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1885.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1887.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1890.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1893.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1906.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1978.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1989.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2014.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2028.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2042.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2077.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2082.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2104.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2107.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2122.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2124.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2135.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2164.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2169.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2177.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2194.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2206.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2208.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2214.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2221.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2246.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2252.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2256.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2261.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2278.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2286.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2293.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2322.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2323.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2351.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2392.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2409.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2410.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2435.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2464.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2473.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2475.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2478.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2490.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2505.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2548.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2560.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2564.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2578.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2592.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2612.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2613.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2616.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2625.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2627.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2634.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2700.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2702.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2710.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2719.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2721.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2733.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2747.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2766.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2789.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2809.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2817.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2819.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2825.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2831.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2833.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2839.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2854.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2856.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2867.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2879.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2894.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2897.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2915.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2928.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2934.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2943.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2954.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2961.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2963.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2966.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2969.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2980.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2996.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3018.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3053.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3070.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3083.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3088.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3092.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3093.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3109.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3157.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3186.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3202.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3216.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3222.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3300.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3345.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3361.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3410.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3447.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3450.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3467.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3480.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3481.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3485.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3486.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3500.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3512.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3571.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3577.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3587.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3591.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3609.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3657.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3662.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3668.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3673.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3733.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3771.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3782.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3788.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3807.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3808.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3813.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3825.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3829.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3833.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3848.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3883.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3899.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3908.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3914.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3922.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3930.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3934.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3946.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3952.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3960.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3981.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3986.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4002.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4034.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4037.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4047.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4074.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4095.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4097.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4117.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4119.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4123.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4128.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4136.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4141.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4142.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4157.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4260.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4261.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4277.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4305.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4336.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4358.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4364.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4394.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4405.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4420.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4432.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4445.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4497.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4499.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4515.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4534.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4538.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4542.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4548.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4615.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4645.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4663.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4665.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4669.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4675.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4681.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4702.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4722.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4736.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4741.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4757.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4775.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4790.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4794.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4795.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4810.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4824.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4831.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4836.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4838.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4869.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4870.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4882.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4890.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4895.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4896.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4946.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5033.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5035.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5036.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5038.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5091.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5125.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5147.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5172.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5191.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5192.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5251.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5252.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5307.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5343.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5347.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5350.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5351.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5376.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5403.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5424.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5431.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5463.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5488.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5522.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5587.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5595.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5597.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5602.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5615.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5659.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5673.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5692.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5696.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5713.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5714.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5718.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5739.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5766.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5796.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5797.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5810.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5846.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5855.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5857.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5862.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5863.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5865.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5879.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5881.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5882.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5922.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5978.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5979.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5987.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6052.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6054.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6084.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6097.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6116.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6137.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6153.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6154.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6172.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6220.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6232.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6256.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6259.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6267.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6300.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6356.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6359.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6414.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6454.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6473.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6495.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6513.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6549.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6569.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6607.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6639.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6643.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6653.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6660.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6664.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6675.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6680.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6694.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6731.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6743.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6769.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6786.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6790.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6799.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6807.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6808.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6859.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6872.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6875.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6876.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6884.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6887.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6900.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6904.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6927.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6944.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6955.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6959.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6971.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6978.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6980.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6989.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7009.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7022.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7025.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7031.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7047.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7059.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7073.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7077.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7087.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7094.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7096.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7103.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7104.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7113.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7137.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7138.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7154.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7155.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7160.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7180.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7215.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7248.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7271.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7296.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7304.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7307.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7321.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7339.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7341.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7367.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7370.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7388.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7406.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7436.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7441.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7446.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7450.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7455.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7457.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7465.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7472.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7489.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7501.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7508.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7523.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7530.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7540.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7555.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7556.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7562.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7575.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7578.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7591.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7619.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7636.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7663.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7686.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7687.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7691.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7708.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7710.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7716.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7741.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7753.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7761.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7784.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7797.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7869.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7875.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7882.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7889.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7893.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7907.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7912.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7927.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7956.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7970.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7990.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8006.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8014.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8036.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8037.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8040.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8061.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8079.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8090.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8124.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8137.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8166.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8188.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8200.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8214.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8215.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8217.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8220.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8272.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8285.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8293.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8295.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8304.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8305.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8325.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8347.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8404.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8407.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8430.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8483.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8561.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8587.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8607.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8610.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8617.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8631.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8670.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8673.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8677.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8683.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8700.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8712.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8717.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8726.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8737.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8771.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8794.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8813.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8825.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8831.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8837.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8838.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8866.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8877.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8885.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8963.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8974.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8983.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8994.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8998.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9033.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9043.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9044.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9053.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9055.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9063.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9086.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9126.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9147.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9151.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9218.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9219.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9224.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9241.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9256.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9263.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9270.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9275.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9315.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9335.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9357.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9364.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9375.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9390.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9402.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9407.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9423.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9436.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9450.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9460.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9521.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9523.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9557.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9561.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9571.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9576.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9592.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9630.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9706.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9721.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9729.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9733.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9749.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9751.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9759.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9785.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9805.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9815.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9823.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9829.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9835.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9837.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9838.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9859.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9898.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9914.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9923.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9949.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9957.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9973.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10046.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10066.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10077.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10084.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10099.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10115.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10122.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10141.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10149.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10155.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10209.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10232.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10242.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10248.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10268.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10276.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10277.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10282.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10348.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10351.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10373.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10374.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10381.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10409.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10420.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10423.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10424.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10426.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10464.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10466.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10470.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10477.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10496.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10516.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10529.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10530.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10534.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10535.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10539.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10578.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10598.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10604.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10618.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10630.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10633.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10637.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10651.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10653.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10671.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10699.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10701.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10709.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10715.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10722.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10750.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10758.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10763.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10775.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10809.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10812.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10813.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10820.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10834.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10904.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10946.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10980.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11025.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11053.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11104.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11116.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11118.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11122.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11131.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11133.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11146.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11153.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11161.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11177.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11184.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11199.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11212.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11214.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11231.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11243.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11245.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11260.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11290.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11297.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11345.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11356.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11391.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11407.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11428.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11442.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11448.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11461.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11476.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11504.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11508.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11509.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11526.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11533.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11550.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11567.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11569.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11582.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11592.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11610.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11626.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11631.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11634.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11649.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11656.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11657.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11689.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11690.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11691.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11727.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11741.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11750.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11778.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11829.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11850.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11865.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11869.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11886.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11924.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11939.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12007.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12029.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12037.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12039.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12051.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12056.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12065.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12073.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12080.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12093.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12101.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12104.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12105.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12107.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12122.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12133.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12136.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12159.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12189.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12200.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12224.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12226.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12252.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12258.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12261.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12269.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12273.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12288.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12297.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12309.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12330.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12332.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst13.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst17.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst19.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst33.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst46.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst80.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst86.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst92.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst109.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst117.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst123.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst144.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst160.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst191.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst210.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst251.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst264.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst265.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst271.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst278.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst281.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst306.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst310.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst342.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst349.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst362.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst430.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst435.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst465.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst466.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst477.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst489.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst491.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst518.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst531.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst551.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst569.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst582.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst597.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst611.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst655.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst667.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst678.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst730.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst734.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst754.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst757.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst770.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst788.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst822.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst830.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst855.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst919.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst936.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst941.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst948.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst967.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst969.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst975.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst999.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1032.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1056.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1058.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1069.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1078.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1108.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1134.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1139.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1153.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1157.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1197.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1215.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1218.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1225.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1228.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1255.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1258.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1284.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1286.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1295.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1311.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1314.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1326.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1344.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1363.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1369.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1377.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1383.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1387.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1410.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1460.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1466.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1479.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1484.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1485.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1490.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1491.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1541.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1553.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1589.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1612.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1652.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1656.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1673.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1676.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1679.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1686.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1718.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1742.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1745.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1748.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1759.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1760.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1776.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1788.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1811.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1853.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1861.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1863.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1885.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1887.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1890.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1893.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1906.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1978.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1989.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2014.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2028.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2042.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2077.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2082.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2104.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2107.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2122.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2124.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2135.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2164.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2169.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2177.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2194.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2206.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2208.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2214.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2221.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2246.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2252.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2256.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2261.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2278.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2286.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2293.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2322.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2323.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2351.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2392.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2409.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2410.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2435.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2464.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2473.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2475.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2478.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2490.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2505.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2548.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2560.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2564.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2578.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2592.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2612.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2613.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2616.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2625.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2627.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2634.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2700.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2702.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2710.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2719.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2721.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2733.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2747.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2766.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2789.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2809.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2817.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2819.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2825.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2831.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2833.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2839.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2854.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2856.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2867.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2879.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2894.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2897.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2915.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2928.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2934.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2943.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2954.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2961.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2963.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2966.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2969.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2980.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2996.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3018.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3053.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3070.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3083.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3088.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3092.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3093.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3109.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3157.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3186.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3202.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3216.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3222.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3300.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3345.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3361.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3410.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3447.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3450.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3467.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3480.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3481.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3485.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3486.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3500.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3512.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3571.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3577.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3587.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3591.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3609.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3657.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3662.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3668.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3673.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3733.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3771.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3782.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3788.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3807.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3808.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3813.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3825.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3829.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3833.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3848.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3883.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3899.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3908.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3914.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3922.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3930.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3934.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3946.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3952.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3960.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3981.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3986.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4002.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4034.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4037.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4047.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4074.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4095.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4097.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4117.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4119.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4123.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4128.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4136.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4141.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4142.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4157.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4260.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4261.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4277.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4305.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4336.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4358.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4364.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4394.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4405.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4420.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4432.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4445.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4497.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4499.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4515.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4534.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4538.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4542.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4548.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4615.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4645.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4663.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4665.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4669.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4675.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4681.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4702.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4722.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4736.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4741.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4757.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4775.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4790.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4794.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4795.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4810.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4824.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4831.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4836.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4869.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4870.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4882.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4890.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4895.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4896.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4946.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5033.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5035.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5036.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5038.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5091.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5125.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5147.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5172.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5191.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5192.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5251.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5252.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5307.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5343.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5347.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5350.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5351.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5376.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5403.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5424.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5431.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5463.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5488.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5522.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5587.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5595.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5597.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5602.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5615.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5659.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5673.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5692.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5696.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5713.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5714.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5718.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5739.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5766.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5796.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5797.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5810.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5846.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5855.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5857.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5862.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5863.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5865.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5879.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5881.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5882.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5922.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5978.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5979.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5987.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6052.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6054.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6084.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6097.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6116.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6137.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6153.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6154.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6172.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6220.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6232.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6256.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6259.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6267.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6300.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6356.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6359.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6414.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6454.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6473.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6495.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6513.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6549.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6569.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6607.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6639.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6643.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6653.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6660.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6664.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6675.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6680.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6694.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6731.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6743.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6769.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6786.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6790.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6799.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6807.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6808.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6859.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6872.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6875.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6876.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6884.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6887.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6900.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6904.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6927.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6944.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6955.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6959.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6971.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6978.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6980.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6989.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7009.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7022.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7025.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7031.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7047.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7059.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7073.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7077.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7087.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7094.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7096.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7103.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7104.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7113.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7137.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7138.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7154.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7155.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7160.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7180.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7215.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7248.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7271.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7296.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7304.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7307.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7321.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7339.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7341.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7367.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7370.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7388.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7406.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7436.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7441.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7446.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7450.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7455.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7457.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7465.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7489.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7501.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7508.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7523.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7530.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7540.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7555.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7556.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7562.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7575.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7578.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7591.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7619.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7636.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7663.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7686.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7687.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7691.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7708.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7710.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7716.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7741.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7753.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7761.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7784.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7797.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7869.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7875.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7882.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7889.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7893.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7912.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7927.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7956.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7970.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7990.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8006.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8014.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8036.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8037.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8040.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8061.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8079.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8090.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8124.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8137.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8166.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8188.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8200.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8214.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8215.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8217.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8220.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8272.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8285.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8293.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8295.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8304.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8305.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8325.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8347.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8404.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8407.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8430.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8483.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8561.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8587.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8607.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8610.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8617.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8631.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8670.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8673.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8677.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8683.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8700.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8712.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8717.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8726.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8737.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8771.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8794.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8813.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8825.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8831.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8837.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8838.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8866.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8877.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8885.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8963.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8974.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8983.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8994.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8998.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9033.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9043.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9044.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9053.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9055.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9063.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9086.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9126.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9147.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9151.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9218.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9219.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9224.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9241.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9256.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9263.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9270.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9275.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9315.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9335.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9357.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9364.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9375.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9390.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9402.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9407.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9423.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9436.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9450.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9460.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9521.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9523.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9557.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9561.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9571.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9576.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9592.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9630.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9706.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9721.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9729.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9733.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9749.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9751.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9759.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9785.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9805.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9815.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9823.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9829.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9835.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9837.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9838.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9859.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9898.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9914.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9923.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9949.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9957.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9973.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10046.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10066.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10077.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10084.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10099.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10115.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10122.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10141.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10149.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10155.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10209.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10232.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10242.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10248.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10268.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10276.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10277.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10282.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10348.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10351.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10373.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10374.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10381.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10409.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10420.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10423.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10424.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10426.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10464.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10466.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10470.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10477.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10496.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10516.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10529.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10530.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10534.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10535.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10539.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10578.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10598.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10604.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10618.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10630.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10633.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10637.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10651.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10653.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10671.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10699.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10701.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10709.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10715.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10722.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10750.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10758.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10763.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10775.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10809.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10812.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10813.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10820.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10834.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10904.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10946.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10980.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11025.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11053.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11104.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11116.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11118.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11122.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11131.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11133.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11146.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11153.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11161.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11177.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11184.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11199.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11212.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11214.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11231.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11243.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11245.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11260.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11290.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11297.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11345.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11356.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11391.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11407.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11428.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11442.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11448.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11461.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11476.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11504.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11508.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11509.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11526.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11533.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11550.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11567.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11569.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11582.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11592.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11610.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11626.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11631.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11634.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11649.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11656.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11657.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11689.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11690.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11691.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11727.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11741.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11750.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11778.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11829.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11850.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11865.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11869.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11886.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11924.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11939.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12007.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12029.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12037.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12039.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12051.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12056.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12065.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12073.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12080.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12093.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12101.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12104.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12105.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12107.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12122.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12133.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12136.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12159.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12189.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12200.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12224.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12226.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12252.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12258.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12261.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12269.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12273.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12288.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12297.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12309.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12330.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12332.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst13.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst17.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst19.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst33.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst46.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst80.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst86.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst92.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst109.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst117.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst123.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst144.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst160.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst191.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst210.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst251.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst264.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst265.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst271.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst278.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst281.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst306.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst310.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst342.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst349.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst362.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst430.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst435.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst465.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst466.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst477.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst489.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst491.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst518.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst531.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst551.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst569.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst582.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst597.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst611.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst655.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst667.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst678.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst730.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst734.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst754.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst757.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst770.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst788.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst822.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst830.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst855.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst919.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst936.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst941.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst948.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst967.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst969.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst975.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst999.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1032.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1056.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1058.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1069.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1078.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1108.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1134.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1139.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1153.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1157.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1197.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1215.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1218.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1225.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1228.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1255.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1258.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1284.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1286.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1295.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1311.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1314.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1326.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1344.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1363.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1369.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1377.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1383.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1387.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1410.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1460.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1466.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1479.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1484.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1485.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1490.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1491.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1541.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1553.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1589.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1612.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1652.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1656.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1673.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1676.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1679.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1686.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1718.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1742.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1745.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1748.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1759.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1760.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1776.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1788.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1811.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1853.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1861.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1863.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1885.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1887.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1890.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1893.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1906.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1978.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1989.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2014.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2028.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2042.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2077.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2082.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2104.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2107.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2122.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2124.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2135.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2164.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2169.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2177.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2194.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2206.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2208.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2214.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2221.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2246.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2252.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2256.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2261.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2278.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2286.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2293.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2322.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2323.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2351.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2392.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2409.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2410.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2435.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2464.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2473.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2475.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2478.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2490.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2505.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2548.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2560.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2564.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2578.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2592.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2612.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2613.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2616.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2625.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2627.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2634.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2700.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2702.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2710.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2719.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2721.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2733.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2747.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2766.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2789.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2809.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2817.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2819.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2825.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2831.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2833.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2839.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2854.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2856.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2867.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2879.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2894.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2897.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2915.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2928.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2934.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2943.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2954.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2961.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2963.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2966.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2969.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2980.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2996.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3018.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3053.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3070.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3083.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3088.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3092.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3093.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3109.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3157.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3186.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3202.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3216.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3222.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3300.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3345.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3361.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3410.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3447.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3450.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3467.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3480.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3481.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3485.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3486.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3500.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3512.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3571.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3577.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3587.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3591.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3609.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3657.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3662.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3668.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3673.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3733.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3771.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3782.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3788.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3807.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3808.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3813.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3825.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3829.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3833.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3848.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3883.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3899.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3908.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3914.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3922.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3930.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3934.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3946.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3952.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3960.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3981.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3986.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4002.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4034.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4037.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4047.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4074.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4095.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4097.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4117.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4119.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4123.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4128.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4136.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4141.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4142.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4157.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4260.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4261.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4277.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4305.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4336.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4358.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4364.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4394.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4405.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4420.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4432.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4445.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4497.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4499.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4515.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4534.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4538.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4542.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4548.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4615.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4645.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4663.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4665.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4669.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4675.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4681.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4702.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4722.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4736.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4741.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4757.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4775.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4790.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4794.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4795.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4810.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4824.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4831.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4836.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4869.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4870.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4882.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4890.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4895.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4896.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4946.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5033.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5035.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5036.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5038.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5091.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5125.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5147.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5172.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5191.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5192.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5251.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5252.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5307.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5343.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5347.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5350.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5351.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5376.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5403.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5424.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5431.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5463.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5488.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5522.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5587.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5595.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5597.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5602.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5615.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5659.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5673.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5692.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5696.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5713.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5714.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5718.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5739.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5766.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5796.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5797.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5810.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5846.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5855.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5857.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5862.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5863.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5865.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5879.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5881.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5882.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5922.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5978.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5979.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5987.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6052.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6054.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6084.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6097.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6116.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6137.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6153.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6154.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6172.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6220.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6232.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6256.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6259.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6267.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6300.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6356.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6359.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6414.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6454.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6473.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6495.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6513.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6549.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6569.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6607.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6639.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6643.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6653.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6660.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6664.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6675.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6680.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6694.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6731.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6743.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6769.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6786.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6790.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6799.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6807.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6808.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6859.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6872.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6875.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6876.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6884.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6887.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6900.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6904.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6927.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6944.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6955.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6959.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6971.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6978.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6980.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6989.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7009.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7022.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7025.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7031.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7047.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7059.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7073.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7077.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7087.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7094.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7096.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7103.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7104.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7113.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7137.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7138.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7154.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7155.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7160.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7180.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7215.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7248.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7271.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7296.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7304.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7307.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7321.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7339.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7341.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7367.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7370.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7388.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7406.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7436.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7441.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7446.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7450.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7455.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7457.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7465.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7489.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7501.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7508.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7523.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7530.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7540.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7555.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7556.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7562.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7575.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7578.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7591.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7619.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7636.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7663.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7686.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7687.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7691.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7708.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7710.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7716.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7741.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7753.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7761.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7784.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7797.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7869.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7875.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7882.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7889.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7893.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7912.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7927.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7956.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7970.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7990.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8006.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8014.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8036.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8037.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8040.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8061.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8079.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8090.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8124.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8137.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8166.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8188.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8200.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8214.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8215.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8217.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8220.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8272.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8285.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8293.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8295.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8304.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8305.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8325.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8347.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8404.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8407.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8430.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8483.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8561.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8587.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8607.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8610.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8617.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8631.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8670.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8673.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8677.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8683.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8700.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8712.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8717.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8726.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8737.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8771.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8794.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8813.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8825.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8831.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8837.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8838.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8866.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8877.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8885.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8963.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8974.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8983.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8994.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8998.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9033.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9043.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9044.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9053.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9055.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9063.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9086.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9126.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9147.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9151.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9218.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9219.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9224.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9241.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9256.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9263.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9270.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9275.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9315.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9335.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9357.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9364.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9375.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9390.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9402.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9407.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9423.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9436.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9450.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9460.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9521.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9523.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9557.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9561.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9571.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9576.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9592.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9630.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9706.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9721.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9729.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9733.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9749.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9751.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9759.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9785.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9805.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9815.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9823.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9829.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9835.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9837.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9838.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9859.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9898.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9914.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9923.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9949.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9957.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9973.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10046.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10066.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10077.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10084.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10099.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10115.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10122.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10141.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10149.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10155.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10209.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10232.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10242.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10248.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10268.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10276.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10277.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10282.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10348.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10351.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10373.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10374.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10381.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10409.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10420.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10423.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10424.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10426.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10464.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10466.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10470.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10477.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10496.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10516.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10529.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10530.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10534.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10535.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10539.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10578.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10598.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10604.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10618.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10630.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10633.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10637.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10651.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10653.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10671.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10699.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10701.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10709.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10715.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10722.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10750.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10758.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10763.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10775.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10809.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10812.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10813.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10820.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10834.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10904.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10946.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10980.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11025.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11053.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11104.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11116.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11118.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11122.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11131.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11133.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11146.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11153.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11161.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11177.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11184.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11199.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11212.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11214.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11231.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11243.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11245.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11260.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11290.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11297.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11345.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11356.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11391.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11407.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11428.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11442.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11448.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11461.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11476.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11504.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11508.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11509.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11526.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11533.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11550.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11567.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11569.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11582.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11592.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11610.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11626.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11631.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11634.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11649.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11656.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11657.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11689.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11690.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11691.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11727.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11741.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11750.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11778.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11829.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11850.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11865.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11869.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11886.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11924.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11939.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12007.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12029.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12037.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12039.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12051.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12056.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12065.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12073.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12080.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12093.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12101.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12104.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12105.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12107.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12122.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12133.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12136.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12159.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12189.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12200.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12224.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12226.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12252.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12258.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12261.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12269.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12273.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12288.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12297.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12309.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12330.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12332.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst13.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst17.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst19.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst33.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst46.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst80.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst86.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst92.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst109.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst117.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst123.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst144.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst160.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst191.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst210.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst251.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst264.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst265.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst271.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst278.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst281.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst306.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst310.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst342.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst349.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst362.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst430.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst435.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst465.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst466.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst477.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst489.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst491.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst518.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst531.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst551.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst569.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst582.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst597.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst611.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst655.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst667.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst678.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst730.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst734.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst754.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst757.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst770.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst788.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst822.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst830.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst855.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst919.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst936.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst941.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst948.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst967.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst969.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst975.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst999.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1032.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1056.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1058.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1069.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1078.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1108.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1134.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1139.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1153.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1157.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1197.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1215.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1218.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1225.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1228.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1255.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1258.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1284.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1286.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1295.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1311.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1314.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1326.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1344.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1363.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1369.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1377.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1383.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1387.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1410.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1460.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1466.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1479.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1484.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1485.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1490.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1491.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1541.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1553.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1589.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1612.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1652.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1656.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1673.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1676.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1679.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1686.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1718.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1742.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1745.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1748.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1759.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1760.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1776.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1788.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1811.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1853.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1861.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1863.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1885.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1887.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1890.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1893.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1906.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1978.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1989.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2014.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2028.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2042.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2077.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2082.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2104.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2107.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2122.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2124.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2135.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2164.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2169.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2177.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2194.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2206.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2208.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2214.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2221.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2246.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2252.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2256.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2261.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2278.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2286.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2293.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2322.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2323.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2351.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2392.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2409.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2410.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2435.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2464.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2473.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2475.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2478.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2490.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2505.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2548.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2560.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2564.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2578.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2592.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2612.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2613.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2616.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2625.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2627.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2634.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2700.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2702.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2710.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2719.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2721.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2733.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2747.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2766.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2789.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2809.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2817.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2819.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2825.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2831.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2833.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2839.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2854.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2856.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2867.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2879.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2894.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2897.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2915.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2928.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2934.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2943.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2954.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2961.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2963.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2966.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2969.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2980.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2996.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3018.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3053.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3070.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3083.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3088.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3092.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3093.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3109.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3157.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3186.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3202.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3216.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3222.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3300.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3345.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3361.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3410.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3447.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3450.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3467.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3480.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3481.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3485.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3486.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3500.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3512.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3571.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3577.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3587.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3591.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3609.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3657.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3662.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3668.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3673.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3733.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3771.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3782.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3788.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3807.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3808.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3813.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3825.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3829.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3833.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3848.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3883.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3899.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3908.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3914.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3922.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3930.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3934.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3946.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3952.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3960.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3981.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3986.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4002.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4034.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4037.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4047.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4074.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4095.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4097.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4117.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4119.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4123.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4128.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4136.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4141.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4142.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4157.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4260.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4261.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4277.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4305.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4336.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4358.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4364.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4394.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4405.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4420.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4432.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4445.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4497.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4499.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4515.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4534.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4538.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4542.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4548.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4615.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4645.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4663.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4665.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4669.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4675.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4681.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4702.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4722.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4736.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4741.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4757.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4775.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4790.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4794.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4795.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4810.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4824.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4831.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4836.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4869.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4870.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4882.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4890.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4895.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4896.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4946.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5033.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5035.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5036.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5038.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5091.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5125.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5147.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5172.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5191.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5192.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5251.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5252.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5307.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5343.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5347.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5350.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5351.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5376.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5403.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5424.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5431.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5463.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5488.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5522.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5587.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5595.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5597.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5602.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5615.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5659.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5673.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5692.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5696.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5713.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5714.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5718.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5739.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5766.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5796.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5797.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5810.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5846.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5855.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5857.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5862.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5863.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5865.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5879.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5881.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5882.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5922.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5978.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5979.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5987.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6052.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6054.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6084.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6097.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6116.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6137.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6153.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6154.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6172.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6220.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6232.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6256.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6259.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6267.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6300.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6356.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6359.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6414.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6454.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6473.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6495.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6513.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6549.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6569.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6607.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6639.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6643.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6653.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6660.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6664.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6675.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6680.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6694.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6731.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6743.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6769.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6786.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6790.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6799.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6807.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6808.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6859.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6872.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6875.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6876.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6884.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6887.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6900.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6904.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6927.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6944.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6955.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6959.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6971.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6978.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6980.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6989.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7009.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7022.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7025.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7031.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7047.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7059.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7073.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7077.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7087.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7094.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7096.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7103.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7104.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7113.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7137.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7138.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7154.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7155.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7160.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7180.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7215.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7248.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7271.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7296.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7304.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7307.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7321.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7339.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7341.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7367.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7370.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7388.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7406.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7436.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7441.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7446.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7450.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7455.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7457.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7465.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7489.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7501.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7508.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7523.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7530.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7540.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7555.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7556.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7562.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7575.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7578.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7591.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7619.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7636.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7663.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7686.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7687.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7691.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7708.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7710.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7716.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7741.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7753.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7761.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7784.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7797.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7869.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7875.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7882.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7889.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7893.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7912.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7927.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7956.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7970.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7990.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8006.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8014.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8036.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8037.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8040.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8061.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8079.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8090.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8124.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8137.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8166.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8188.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8200.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8214.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8215.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8217.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8220.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8272.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8285.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8293.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8295.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8304.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8305.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8325.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8347.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8404.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8407.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8430.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8483.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8561.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8587.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8607.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8610.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8617.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8631.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8670.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8673.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8677.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8683.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8700.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8712.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8717.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8726.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8737.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8771.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8794.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8813.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8825.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8831.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8837.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8838.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8866.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8877.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8885.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8963.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8974.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8983.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8994.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8998.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9033.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9043.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9044.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9053.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9055.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9063.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9086.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9126.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9147.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9151.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9218.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9219.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9224.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9241.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9256.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9263.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9270.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9275.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9315.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9335.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9357.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9364.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9375.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9390.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9402.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9407.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9423.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9436.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9450.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9460.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9521.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9523.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9557.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9561.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9571.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9576.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9592.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9630.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9706.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9721.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9729.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9733.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9749.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9751.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9759.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9785.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9805.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9815.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9823.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9829.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9835.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9837.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9838.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9859.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9898.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9914.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9923.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9949.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9957.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9973.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10046.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10066.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10077.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10084.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10099.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10115.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10122.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10141.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10149.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10155.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10209.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10232.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10242.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10248.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10268.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10276.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10277.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10282.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10348.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10351.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10373.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10374.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10381.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10409.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10420.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10423.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10424.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10426.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10464.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10466.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10470.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10477.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10496.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10516.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10529.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10530.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10534.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10535.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10539.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10578.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10598.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10604.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10618.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10630.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10633.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10637.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10651.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10653.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10671.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10699.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10701.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10709.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10715.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10722.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10750.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10758.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10763.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10775.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10809.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10812.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10813.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10820.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10834.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10904.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10946.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10980.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11025.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11053.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11104.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11116.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11118.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11122.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11131.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11133.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11146.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11153.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11161.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11177.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11184.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11199.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11212.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11214.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11231.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11243.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11245.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11260.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11290.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11297.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11345.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11356.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11391.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11407.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11428.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11442.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11448.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11461.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11476.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11504.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11508.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11509.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11526.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11533.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11550.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11567.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11569.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11582.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11592.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11610.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11626.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11631.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11634.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11649.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11656.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11657.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11689.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11690.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11691.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11727.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11741.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11750.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11778.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11829.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11850.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11865.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11869.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11886.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11924.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11939.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12007.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12029.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12037.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12039.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12051.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12056.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12065.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12073.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12080.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12093.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12101.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12104.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12105.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12107.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12122.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12133.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12136.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12159.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12189.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12200.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12224.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12226.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12252.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12258.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12261.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12269.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12273.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12288.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12297.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12309.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12330.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12332.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst13.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst17.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst19.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst33.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst46.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst80.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst86.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst92.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst109.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst117.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst123.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst144.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst160.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst191.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst210.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst251.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst264.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst265.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst271.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst278.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst281.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst306.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst310.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst342.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst349.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst362.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst430.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst435.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst465.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst466.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst477.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst489.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst491.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst518.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst531.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst551.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst569.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst582.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst597.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst611.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst655.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst667.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst678.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst730.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst734.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst754.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst757.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst770.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst788.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst822.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst830.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst855.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst919.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst936.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst941.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst948.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst967.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst969.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst975.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst999.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1032.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1056.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1058.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1069.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1078.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1108.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1134.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1139.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1153.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1157.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1197.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1215.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1218.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1225.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1228.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1255.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1258.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1284.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1286.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1295.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1311.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1314.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1326.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1344.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1363.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1369.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1377.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1383.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1387.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1410.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1460.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1466.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1479.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1484.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1485.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1490.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1491.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1541.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1553.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1589.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1612.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1652.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1656.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1673.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1676.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1679.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1686.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1718.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1742.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1745.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1748.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1759.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1760.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1776.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1788.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1811.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1853.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1861.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1863.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1885.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1887.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1890.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1893.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1906.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1978.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1989.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2014.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2028.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2042.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2077.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2082.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2104.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2107.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2122.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2124.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2135.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2164.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2169.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2177.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2194.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2206.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2208.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2214.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2221.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2246.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2252.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2256.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2261.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2278.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2286.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2293.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2322.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2323.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2351.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2392.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2409.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2410.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2435.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2464.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2473.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2475.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2478.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2490.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2505.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2548.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2560.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2564.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2578.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2592.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2612.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2613.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2616.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2625.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2627.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2634.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2700.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2702.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2710.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2719.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2721.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2733.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2747.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2766.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2789.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2809.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2817.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2819.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2825.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2831.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2833.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2839.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2854.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2856.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2867.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2879.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2894.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2897.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2915.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2928.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2934.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2943.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2954.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2961.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2963.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2966.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2969.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2980.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2996.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3018.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3053.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3070.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3083.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3088.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3092.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3093.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3109.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3157.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3186.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3202.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3216.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3222.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3300.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3345.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3361.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3410.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3447.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3450.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3467.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3480.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3481.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3485.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3486.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3500.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3512.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3571.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3577.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3587.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3591.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3609.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3657.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3662.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3668.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3673.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3733.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3771.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3782.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3788.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3807.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3808.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3813.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3825.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3829.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3833.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3848.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3883.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3899.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3908.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3914.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3922.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3930.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3934.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3946.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3952.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3960.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3981.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3986.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4002.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4034.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4037.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4047.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4074.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4095.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4097.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4117.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4119.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4123.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4128.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4136.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4141.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4142.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4157.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4260.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4261.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4277.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4305.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4336.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4358.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4364.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4394.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4405.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4420.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4432.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4445.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4497.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4499.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4515.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4534.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4538.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4542.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4548.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4615.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4645.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4663.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4665.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4669.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4675.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4681.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4702.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4722.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4736.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4741.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4757.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4775.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4790.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4794.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4795.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4810.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4824.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4831.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4836.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4869.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4870.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4882.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4890.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4895.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4896.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4946.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5033.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5035.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5036.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5038.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5091.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5125.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5147.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5172.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5191.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5192.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5251.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5252.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5307.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5343.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5347.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5350.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5351.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5376.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5403.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5424.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5431.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5463.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5488.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5522.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5587.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5595.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5597.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5602.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5615.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5659.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5673.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5692.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5696.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5713.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5714.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5718.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5739.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5766.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5796.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5797.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5810.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5846.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5855.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5857.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5862.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5863.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5865.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5879.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5881.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5882.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5922.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5978.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5979.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5987.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6052.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6054.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6084.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6097.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6116.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6137.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6153.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6154.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6172.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6220.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6232.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6256.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6259.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6267.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6300.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6356.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6359.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6414.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6454.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6473.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6495.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6513.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6549.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6569.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6607.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6639.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6643.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6653.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6660.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6664.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6675.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6680.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6694.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6731.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6743.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6769.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6786.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6790.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6799.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6807.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6808.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6859.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6872.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6875.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6876.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6884.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6887.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6900.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6904.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6927.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6944.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6955.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6959.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6971.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6978.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6980.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6989.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7009.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7022.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7025.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7031.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7047.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7059.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7073.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7077.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7087.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7094.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7096.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7103.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7104.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7113.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7137.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7138.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7154.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7155.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7160.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7180.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7215.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7248.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7271.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7296.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7304.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7307.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7321.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7339.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7341.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7367.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7370.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7388.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7406.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7436.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7441.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7446.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7450.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7455.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7457.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7465.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7489.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7501.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7508.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7523.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7530.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7540.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7555.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7556.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7562.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7575.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7578.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7591.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7619.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7636.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7663.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7686.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7687.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7691.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7708.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7710.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7716.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7741.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7753.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7761.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7784.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7797.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7869.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7875.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7882.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7889.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7893.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7912.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7927.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7956.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7970.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7990.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8006.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8014.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8036.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8037.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8040.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8061.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8079.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8090.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8124.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8137.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8166.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8188.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8200.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8214.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8215.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8217.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8220.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8272.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8285.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8293.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8295.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8304.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8305.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8325.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8347.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8404.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8407.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8430.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8483.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8561.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8587.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8607.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8610.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8617.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8631.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8670.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8673.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8677.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8683.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8700.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8712.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8717.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8726.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8737.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8771.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8794.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8813.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8825.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8831.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8837.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8838.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8866.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8877.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8885.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8963.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8974.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8983.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8994.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8998.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9033.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9043.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9044.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9053.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9055.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9063.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9086.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9126.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9147.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9151.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9218.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9219.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9224.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9241.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9256.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9263.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9270.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9275.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9315.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9335.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9357.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9364.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9375.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9390.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9402.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9407.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9423.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9436.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9450.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9460.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9521.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9523.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9557.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9561.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9571.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9576.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9592.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9630.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9706.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9721.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9729.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9733.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9749.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9751.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9759.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9785.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9805.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9815.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9823.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9829.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9835.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9837.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9838.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9859.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9898.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9914.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9923.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9949.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9957.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9973.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10046.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10066.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10077.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10084.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10099.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10115.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10122.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10141.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10149.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10155.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10209.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10232.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10242.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10248.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10268.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10276.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10277.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10282.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10348.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10351.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10373.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10374.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10381.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10409.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10420.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10423.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10424.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10426.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10464.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10466.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10470.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10477.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10496.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10516.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10529.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10530.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10534.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10535.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10539.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10578.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10598.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10604.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10618.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10630.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10633.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10637.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10651.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10653.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10671.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10699.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10701.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10709.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10715.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10722.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10750.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10758.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10763.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10775.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10809.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10812.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10813.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10820.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10834.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10904.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10946.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10980.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11025.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11053.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11104.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11116.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11118.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11122.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11131.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11133.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11146.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11153.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11161.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11177.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11184.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11199.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11212.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11214.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11231.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11243.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11245.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11260.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11290.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11297.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11345.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11356.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11391.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11407.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11428.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11442.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11448.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11461.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11476.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11504.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11508.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11509.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11526.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11533.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11550.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11567.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11569.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11582.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11592.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11610.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11626.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11631.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11634.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11649.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11656.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11657.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11689.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11690.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11691.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11727.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11741.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11750.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11778.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11829.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11850.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11865.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11869.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11886.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11924.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11939.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12007.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12029.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12037.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12039.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12051.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12056.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12065.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12073.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12080.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12093.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12101.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12104.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12105.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12107.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12122.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12133.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12136.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12159.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12189.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12200.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12224.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12226.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12252.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12258.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12261.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12269.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12273.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12288.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12297.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12309.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12330.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12332.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst13.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst17.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst19.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst33.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst46.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst80.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst86.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst92.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst109.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst117.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst123.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst144.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst160.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst191.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst210.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst251.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst264.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst265.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst271.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst278.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst281.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst306.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst310.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst342.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst349.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst362.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst430.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst435.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst465.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst466.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst477.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst489.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst491.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst518.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst531.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst551.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst569.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst582.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst597.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst611.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst655.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst667.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst678.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst730.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst734.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst754.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst757.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst770.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst788.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst822.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst830.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst855.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst919.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst936.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst941.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst948.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst967.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst969.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst975.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst999.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1032.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1056.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1058.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1069.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1078.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1108.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1134.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1139.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1153.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1157.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1197.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1215.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1218.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1225.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1228.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1255.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1258.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1284.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1286.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1295.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1311.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1314.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1326.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1344.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1363.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1369.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1377.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1383.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1387.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1410.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1460.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1466.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1479.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1484.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1485.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1490.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1491.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1541.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1553.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1589.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1612.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1652.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1656.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1673.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1676.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1679.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1686.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1718.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1742.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1745.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1748.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1759.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1760.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1776.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1788.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1811.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1853.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1861.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1863.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1885.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1887.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1890.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1893.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1906.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1978.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1989.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2014.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2028.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2042.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2077.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2082.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2104.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2107.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2122.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2124.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2135.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2164.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2169.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2177.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2194.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2206.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2208.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2214.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2221.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2246.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2252.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2256.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2261.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2278.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2286.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2293.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2322.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2323.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2351.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2392.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2409.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2410.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2435.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2464.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2473.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2475.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2478.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2490.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2505.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2548.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2560.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2564.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2578.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2592.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2612.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2613.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2616.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2625.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2627.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2634.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2700.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2702.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2710.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2719.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2721.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2733.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2747.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2766.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2789.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2809.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2817.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2819.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2825.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2831.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2833.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2839.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2854.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2856.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2867.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2879.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2894.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2897.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2915.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2928.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2934.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2943.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2954.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2961.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2963.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2966.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2969.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2980.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2996.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3018.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3053.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3070.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3083.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3088.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3092.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3093.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3109.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3157.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3186.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3202.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3216.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3222.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3300.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3345.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3361.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3410.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3447.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3450.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3467.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3480.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3481.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3485.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3486.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3500.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3512.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3571.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3577.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3587.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3591.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3609.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3657.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3662.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3668.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3673.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3733.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3771.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3782.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3788.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3807.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3808.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3813.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3825.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3829.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3833.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3848.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3883.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3899.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3908.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3914.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3922.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3930.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3934.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3946.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3952.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3960.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3981.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3986.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4002.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4034.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4037.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4047.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4074.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4095.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4097.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4117.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4119.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4123.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4128.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4136.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4141.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4142.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4157.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4260.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4261.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4277.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4305.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4336.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4358.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4364.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4394.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4405.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4420.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4432.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4445.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4497.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4499.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4515.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4534.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4538.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4542.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4548.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4615.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4645.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4663.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4665.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4669.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4675.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4681.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4702.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4722.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4736.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4741.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4757.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4775.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4790.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4794.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4795.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4810.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4824.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4831.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4836.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4869.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4870.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4882.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4890.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4895.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4896.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4946.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5033.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5035.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5036.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5038.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5091.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5125.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5147.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5172.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5191.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5192.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5251.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5252.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5307.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5343.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5347.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5350.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5351.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5376.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5403.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5424.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5431.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5463.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5488.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5522.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5587.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5595.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5597.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5602.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5615.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5659.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5673.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5692.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5696.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5713.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5714.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5718.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5739.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5766.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5796.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5797.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5810.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5846.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5855.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5857.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5862.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5863.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5865.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5879.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5881.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5882.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5922.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5978.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5979.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5987.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6052.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6054.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6084.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6097.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6116.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6137.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6153.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6154.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6172.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6220.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6232.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6256.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6259.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6267.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6300.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6356.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6359.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6414.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6454.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6473.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6495.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6513.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6549.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6569.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6607.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6639.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6643.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6653.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6660.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6664.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6675.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6680.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6694.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6731.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6743.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6769.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6786.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6790.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6799.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6807.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6808.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6859.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6872.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6875.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6876.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6884.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6887.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6900.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6904.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6927.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6944.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6955.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6959.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6971.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6978.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6980.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6989.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7009.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7022.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7025.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7031.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7047.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7059.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7073.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7077.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7087.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7094.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7096.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7103.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7104.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7113.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7137.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7138.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7154.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7155.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7160.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7180.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7215.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7248.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7271.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7296.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7304.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7307.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7321.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7339.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7341.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7367.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7370.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7388.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7406.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7436.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7441.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7446.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7450.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7455.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7457.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7465.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7489.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7501.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7508.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7523.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7530.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7540.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7555.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7556.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7562.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7575.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7578.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7591.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7619.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7636.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7663.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7686.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7687.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7691.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7708.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7710.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7716.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7741.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7753.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7761.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7784.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7797.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7869.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7875.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7882.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7889.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7893.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7912.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7927.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7956.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7970.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7990.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8006.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8014.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8036.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8037.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8040.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8061.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8079.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8090.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8124.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8137.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8166.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8188.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8200.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8214.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8215.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8217.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8220.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8272.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8285.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8293.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8295.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8304.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8305.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8325.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8347.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8404.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8407.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8430.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8483.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8561.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8587.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8607.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8610.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8617.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8631.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8670.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8673.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8677.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8683.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8700.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8712.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8717.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8726.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8737.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8771.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8794.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8813.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8825.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8831.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8837.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8838.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8866.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8877.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8885.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8963.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8974.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8983.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8994.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8998.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9033.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9043.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9044.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9053.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9055.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9063.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9086.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9126.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9147.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9151.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9218.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9219.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9224.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9241.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9256.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9263.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9270.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9275.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9315.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9335.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9357.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9364.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9375.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9390.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9402.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9407.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9423.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9436.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9450.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9460.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9521.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9523.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9557.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9561.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9571.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9576.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9592.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9630.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9706.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9721.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9729.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9733.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9749.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9751.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9759.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9785.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9805.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9815.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9823.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9829.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9835.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9837.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9838.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9859.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9898.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9914.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9923.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9949.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9957.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9973.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10046.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10066.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10077.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10084.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10099.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10115.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10122.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10141.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10149.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10155.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10209.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10232.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10242.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10248.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10268.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10276.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10277.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10282.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10348.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10351.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10373.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10374.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10381.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10409.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10420.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10423.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10424.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10426.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10464.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10466.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10470.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10477.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10496.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10516.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10529.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10530.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10534.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10535.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10539.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10578.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10598.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10604.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10618.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10630.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10633.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10637.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10651.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10653.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10671.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10699.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10701.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10709.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10715.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10722.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10750.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10758.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10763.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10775.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10809.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10812.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10813.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10820.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10834.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10904.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10946.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10980.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11025.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11053.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11104.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11116.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11118.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11122.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11131.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11133.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11146.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11153.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11161.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11177.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11184.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11199.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11212.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11214.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11231.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11243.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11245.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11260.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11290.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11297.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11345.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11356.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11391.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11407.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11428.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11442.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11448.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11461.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11476.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11504.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11508.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11509.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11526.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11533.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11550.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11567.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11569.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11582.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11592.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11610.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11626.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11631.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11634.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11649.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11656.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11657.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11689.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11690.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11691.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11727.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11741.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11750.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11778.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11829.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11850.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11865.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11869.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11886.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11924.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11939.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12007.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12029.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12037.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12039.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12051.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12056.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12065.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12073.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12080.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12093.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12101.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12104.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12105.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12107.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12122.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12133.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12136.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12159.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12189.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12200.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12224.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12226.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12252.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12258.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12261.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12269.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12273.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12288.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12297.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12309.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12330.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12332.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst13.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst17.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst19.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst33.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst46.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst80.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst86.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst92.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst109.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst117.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst123.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst144.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst160.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst191.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst210.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst251.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst264.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst265.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst271.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst278.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst281.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst306.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst310.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst342.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst349.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst362.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst430.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst435.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst465.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst466.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst477.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst489.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst491.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst518.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst531.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst551.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst569.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst582.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst597.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst611.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst655.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst667.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst678.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst730.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst734.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst754.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst757.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst770.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst788.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst822.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst830.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst855.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst919.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst936.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst941.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst948.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst967.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst969.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst975.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst999.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1032.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1056.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1058.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1069.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1078.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1108.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1134.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1139.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1153.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1157.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1197.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1215.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1218.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1225.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1228.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1255.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1258.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1284.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1286.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1295.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1311.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1314.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1326.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1344.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1363.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1369.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1377.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1383.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1387.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1410.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1460.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1466.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1479.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1484.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1485.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1490.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1491.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1541.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1553.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1589.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1612.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1652.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1656.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1673.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1676.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1679.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1686.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1718.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1742.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1745.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1748.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1759.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1760.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1776.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1788.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1811.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1853.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1861.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1863.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1885.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1887.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1890.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1893.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1906.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1978.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1989.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2014.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2028.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2042.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2077.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2082.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2104.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2107.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2122.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2124.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2135.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2164.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2169.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2177.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2194.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2206.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2208.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2214.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2221.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2246.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2252.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2256.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2261.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2278.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2286.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2293.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2322.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2323.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2351.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2392.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2409.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2410.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2435.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2464.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2473.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2475.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2478.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2490.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2505.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2548.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2560.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2564.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2578.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2592.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2612.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2613.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2616.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2625.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2627.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2634.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2700.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2702.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2710.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2719.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2721.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2733.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2747.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2766.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2789.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2809.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2817.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2819.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2825.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2831.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2833.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2839.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2854.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2856.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2867.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2879.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2894.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2897.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2915.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2928.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2934.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2943.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2954.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2961.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2963.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2966.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2969.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2980.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2996.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3018.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3053.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3070.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3083.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3088.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3092.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3093.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3109.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3157.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3186.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3202.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3216.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3222.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3300.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3345.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3361.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3410.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3447.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3450.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3467.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3480.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3481.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3485.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3486.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3500.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3512.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3571.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3577.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3587.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3591.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3609.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3657.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3662.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3668.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3673.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3733.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3771.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3782.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3788.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3807.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3808.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3813.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3825.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3829.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3833.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3848.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3883.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3899.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3908.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3914.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3922.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3930.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3934.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3946.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3952.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3960.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3981.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3986.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4002.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4034.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4037.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4047.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4074.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4095.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4097.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4117.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4119.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4123.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4128.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4136.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4141.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4142.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4157.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4260.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4261.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4277.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4305.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4336.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4358.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4364.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4394.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4405.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4420.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4432.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4445.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4497.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4499.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4515.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4534.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4538.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4542.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4548.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4615.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4645.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4663.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4665.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4669.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4675.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4681.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4702.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4722.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4736.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4741.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4757.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4775.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4790.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4794.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4795.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4810.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4824.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4831.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4836.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4869.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4870.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4882.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4890.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4895.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4896.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4946.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5033.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5035.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5036.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5038.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5091.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5125.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5147.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5172.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5191.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5192.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5251.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5252.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5307.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5343.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5347.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5350.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5351.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5376.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5403.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5424.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5431.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5463.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5488.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5522.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5587.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5595.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5597.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5602.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5615.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5659.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5673.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5692.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5696.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5713.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5714.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5718.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5739.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5766.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5796.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5797.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5810.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5846.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5855.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5857.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5862.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5863.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5865.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5879.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5881.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5882.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5922.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5978.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5979.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5987.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6052.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6054.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6084.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6097.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6116.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6137.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6153.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6154.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6172.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6220.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6232.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6256.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6259.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6267.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6300.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6356.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6359.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6414.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6454.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6473.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6495.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6513.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6549.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6569.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6607.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6639.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6643.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6653.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6660.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6664.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6675.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6680.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6694.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6731.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6743.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6769.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6786.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6790.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6799.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6807.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6808.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6859.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6872.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6875.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6876.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6884.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6887.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6900.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6904.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6927.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6944.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6955.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6959.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6971.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6978.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6980.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6989.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7009.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7022.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7025.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7031.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7047.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7059.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7073.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7077.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7087.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7094.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7096.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7103.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7104.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7113.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7137.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7138.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7154.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7155.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7160.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7180.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7215.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7248.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7271.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7296.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7304.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7307.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7321.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7339.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7341.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7367.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7370.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7388.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7406.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7436.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7441.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7446.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7450.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7455.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7457.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7465.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7489.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7501.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7508.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7523.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7530.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7540.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7555.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7556.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7562.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7575.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7578.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7591.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7619.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7636.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7663.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7686.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7687.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7691.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7708.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7710.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7716.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7741.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7753.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7761.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7784.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7797.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7869.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7875.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7882.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7889.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7893.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7912.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7927.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7956.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7970.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7990.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8006.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8014.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8036.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8037.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8040.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8061.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8079.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8090.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8124.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8137.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8166.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8188.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8200.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8214.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8215.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8217.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8220.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8272.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8285.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8293.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8295.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8304.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8305.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8325.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8347.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8404.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8407.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8430.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8483.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8561.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8587.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8607.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8610.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8617.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8631.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8670.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8673.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8677.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8683.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8700.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8712.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8717.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8726.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8737.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8771.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8794.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8813.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8825.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8831.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8837.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8838.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8866.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8877.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8885.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8963.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8974.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8983.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8994.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8998.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9033.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9043.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9044.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9053.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9055.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9063.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9086.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9126.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9147.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9151.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9218.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9219.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9224.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9241.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9256.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9263.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9270.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9275.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9315.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9335.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9357.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9364.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9375.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9390.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9402.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9407.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9423.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9436.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9450.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9460.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9521.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9523.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9557.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9561.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9571.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9576.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9592.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9630.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9706.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9721.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9729.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9733.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9749.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9751.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9759.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9785.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9805.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9815.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9823.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9829.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9835.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9837.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9838.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9859.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9898.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9914.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9923.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9949.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9957.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9973.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10046.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10066.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10077.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10084.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10099.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10115.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10122.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10141.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10149.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10155.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10209.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10232.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10242.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10248.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10268.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10276.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10277.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10282.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10348.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10351.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10373.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10374.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10381.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10409.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10420.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10423.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10424.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10426.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10464.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10466.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10470.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10477.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10496.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10516.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10529.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10530.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10534.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10535.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10539.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10578.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10598.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10604.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10618.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10630.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10633.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10637.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10651.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10653.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10671.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10699.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10701.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10709.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10715.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10722.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10750.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10758.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10763.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10775.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10809.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10812.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10813.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10820.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10834.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10904.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10946.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10980.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11025.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11053.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11104.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11116.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11118.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11122.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11131.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11133.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11146.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11153.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11161.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11177.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11184.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11199.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11212.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11214.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11231.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11243.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11245.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11260.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11290.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11297.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11345.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11356.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11391.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11407.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11428.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11442.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11448.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11461.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11476.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11504.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11508.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11509.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11526.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11533.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11550.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11567.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11569.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11582.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11592.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11610.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11626.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11631.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11634.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11649.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11656.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11657.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11689.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11690.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11691.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11727.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11741.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11750.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11778.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11829.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11850.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11865.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11869.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11886.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11924.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11939.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12007.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12029.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12037.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12039.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12051.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12056.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12065.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12073.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12080.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12093.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12101.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12104.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12105.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12107.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12122.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12133.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12136.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12159.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12189.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12200.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12224.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12226.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12252.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12258.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12261.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12269.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12273.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12288.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12297.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12309.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12330.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12332.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst13.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst17.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst19.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst33.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst46.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst80.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst86.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst92.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst109.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst117.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst123.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst144.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst160.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst191.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst202.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst210.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst251.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst264.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst265.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst271.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst278.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst281.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst306.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst310.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst316.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst342.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst349.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst362.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst430.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst435.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst465.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst466.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst477.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst489.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst491.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst518.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst531.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst551.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst569.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst582.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst597.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst611.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst614.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst655.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst667.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst678.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst699.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst730.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst734.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst754.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst757.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst770.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst788.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst822.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst830.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst855.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst866.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst919.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst936.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst941.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst948.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst962.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst967.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst969.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst975.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst999.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1026.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1032.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1056.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1058.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1069.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1078.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1108.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1134.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1139.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1153.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1157.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1184.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1197.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1215.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1218.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1225.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1228.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1233.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1255.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1258.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1269.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1284.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1286.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1295.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1311.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1314.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1325.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1326.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1344.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1363.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1369.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1377.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1383.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1387.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1410.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1426.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1428.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1460.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1466.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1479.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1484.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1485.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1490.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1491.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1502.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1529.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1541.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1553.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1589.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1599.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1612.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1652.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1656.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1673.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1676.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1679.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1684.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1686.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1718.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1720.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1742.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1745.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1748.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1759.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1760.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1776.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1788.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1811.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1821.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1853.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1861.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1863.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1885.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1887.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1890.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1893.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1906.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1978.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1989.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2014.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2028.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2042.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2077.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2082.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2104.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2107.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2122.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2124.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2135.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2164.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2169.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2177.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2194.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2206.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2208.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2214.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2221.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2246.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2252.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2256.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2261.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2278.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2286.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2293.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2322.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2323.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2351.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2392.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2409.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2410.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2435.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2464.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2473.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2475.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2478.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2490.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2505.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2548.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2560.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2564.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2573.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2578.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2592.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2612.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2613.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2616.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2625.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2627.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2634.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2700.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2702.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2710.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2719.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2721.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2733.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2747.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2766.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2789.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2809.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2817.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2819.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2825.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2826.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2831.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2833.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2839.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2854.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2856.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2867.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2879.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2894.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2897.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2915.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2928.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2934.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2943.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2954.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2961.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2963.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2966.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2969.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2980.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2996.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3018.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3053.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3070.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3083.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3088.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3092.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3093.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3109.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3157.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3186.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3202.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3216.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3222.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3236.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3300.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3314.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3330.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3337.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3345.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3361.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3410.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3447.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3450.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3467.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3480.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3481.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3485.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3486.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3500.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3512.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3555.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3570.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3571.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3577.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3587.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3591.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3609.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3621.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3657.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3662.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3668.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3670.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3673.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3733.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3752.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3771.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3782.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3788.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3807.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3808.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3813.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3816.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3825.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3829.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3833.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3848.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3883.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3899.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3908.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3914.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3922.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3930.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3934.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3946.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3952.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3955.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3960.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3981.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3986.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4002.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4003.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4034.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4037.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4047.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4074.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4095.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4097.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4117.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4119.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4123.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4128.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4136.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4141.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4142.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4157.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4214.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4260.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4261.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4277.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4305.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4336.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4358.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4364.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4394.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4405.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4420.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4432.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4445.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4497.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4499.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4500.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4505.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4515.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4534.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4538.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4542.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4548.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4615.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4617.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4645.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4663.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4665.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4669.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4675.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4681.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4702.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4722.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4736.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4741.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4757.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4762.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4775.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4787.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4790.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4794.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4795.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4806.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4810.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4824.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4831.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4836.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4838.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4869.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4870.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4882.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4890.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4895.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4896.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4946.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4997.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5033.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5035.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5036.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5038.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5077.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5091.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5114.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5125.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5133.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5147.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5172.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5191.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5192.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5250.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5251.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5252.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5298.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5307.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5329.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5343.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5347.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5350.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5351.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5376.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5403.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5416.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5424.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5431.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5463.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5476.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5488.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5522.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5587.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5595.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5597.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5602.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5603.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5615.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5659.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5664.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5673.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5690.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5692.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5696.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5713.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5714.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5716.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5718.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5739.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5766.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5796.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5797.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5804.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5810.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5812.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5834.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5846.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5855.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5857.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5862.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5863.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5865.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5873.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5879.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5881.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5882.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5922.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5978.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5979.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5987.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6052.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6054.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6065.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6084.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6085.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6097.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6106.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6116.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6137.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6153.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6154.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6172.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6220.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6232.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6256.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6258.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6259.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6267.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6300.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6340.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6356.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6359.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6414.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6454.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6459.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6473.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6495.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6513.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6549.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6561.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6569.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6598.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6606.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6607.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6639.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6643.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6650.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6653.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6660.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6664.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6675.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6680.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6694.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6731.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6743.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6764.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6769.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6786.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6790.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6799.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6807.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6808.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6827.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6830.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6859.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6872.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6875.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6876.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6884.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6887.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6900.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6904.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6906.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6927.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6944.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6955.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6959.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6971.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6978.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6980.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6989.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7009.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7022.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7023.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7025.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7031.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7047.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7050.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7059.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7073.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7077.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7087.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7094.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7096.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7103.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7104.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7113.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7137.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7138.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7154.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7155.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7160.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7180.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7215.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7248.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7271.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7296.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7304.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7307.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7321.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7339.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7341.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7367.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7370.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7388.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7406.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7436.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7441.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7446.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7450.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7455.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7457.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7465.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7472.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7489.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7501.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7508.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7523.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7530.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7540.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7555.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7556.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7562.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7575.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7578.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7591.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7608.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7619.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7632.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7636.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7663.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7681.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7686.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7687.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7691.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7708.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7710.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7716.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7741.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7753.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7761.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7784.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7797.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7869.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7875.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7881.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7882.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7889.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7893.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7907.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7912.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7927.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7956.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7970.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7977.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7990.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8006.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8014.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8036.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8037.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8040.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8061.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8079.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8090.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8124.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8132.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8137.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8166.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8188.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8200.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8208.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8214.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8215.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8217.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8220.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8253.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8272.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8285.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8293.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8295.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8304.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8305.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8325.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8347.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8365.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8401.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8404.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8407.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8430.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8431.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8445.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8483.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8561.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8564.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8587.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8600.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8607.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8609.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8610.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8617.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8631.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8635.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8670.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8673.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8677.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8681.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8683.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8688.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8700.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8706.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8712.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8717.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8726.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8737.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8764.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8771.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8794.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8800.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8803.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8813.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8825.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8831.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8837.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8838.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8866.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8870.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8877.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8885.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8903.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8963.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8967.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8971.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8974.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8983.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8994.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8998.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9030.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9033.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9043.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9044.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9053.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9055.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9063.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9072.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9081.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9086.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9111.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9126.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9147.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9151.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9173.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9208.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9211.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9218.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9219.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9223.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9224.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9228.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9235.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9241.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9256.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9263.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9270.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9275.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9315.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9335.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9357.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9364.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9368.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9375.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9390.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9402.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9407.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9423.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9436.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9437.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9450.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9460.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9480.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9508.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9521.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9523.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9557.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9561.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9571.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9576.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9592.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9620.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9630.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9684.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9696.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9706.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9721.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9729.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9733.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9749.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9751.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9759.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9785.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9805.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9815.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9823.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9829.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9835.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9837.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9838.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9859.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9898.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9914.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9923.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9949.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9956.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9957.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9960.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9970.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9973.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10004.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10021.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10046.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10066.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10077.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10084.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10099.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10115.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10122.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10129.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10141.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10149.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10151.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10155.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10209.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10232.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10242.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10248.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10256.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10268.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10276.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10277.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10282.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10285.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10348.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10351.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10373.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10374.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10381.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10383.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10409.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10420.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10423.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10424.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10426.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10464.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10466.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10470.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10477.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10496.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10516.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10529.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10530.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10534.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10535.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10539.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10565.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10578.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10598.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10604.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10618.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10630.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10632.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10633.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10637.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10651.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10653.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10662.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10671.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10699.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10701.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10709.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10715.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10722.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10750.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10758.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10760.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10763.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10775.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10798.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10809.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10812.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10813.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10820.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10834.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10840.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10904.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10946.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10979.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10980.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10981.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11011.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11018.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11025.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11048.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11053.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11090.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11104.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11116.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11118.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11122.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11131.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11133.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11146.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11153.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11161.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11177.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11184.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11199.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11205.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11212.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11214.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11231.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11243.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11245.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11260.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11290.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11297.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11327.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11336.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11345.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11356.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11391.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11407.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11411.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11428.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11442.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11448.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11461.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11476.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11482.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11484.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11504.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11508.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11509.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11525.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11526.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11533.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11550.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11567.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11569.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11580.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11582.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11588.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11592.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11610.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11624.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11626.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11631.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11634.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11639.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11649.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11654.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11656.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11657.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11689.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11690.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11691.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11710.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11727.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11741.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11744.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11750.xdti_28hc_10t_30_soffqbcka01	41.67			41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11778.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11802.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11829.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11832.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11850.xdti_28hc_10t_30_soffqbcka01	33.33			33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11865.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11869.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11886.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11913.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11924.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11939.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11984.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12007.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12029.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12037.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12039.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12047.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12051.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12056.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12065.xdti_28hc_10t_30_soffqbcka01	16.67			16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12073.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12080.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12093.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12101.xdti_28hc_10t_30_soffqbcka01	20.83			20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12104.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12105.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12107.xdti_28hc_10t_30_soffqbcka01	29.17			29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12122.xdti_28hc_10t_30_soffqbcka01	4.17			4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12133.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12134.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12136.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12159.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12189.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12200.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12224.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12226.xdti_28hc_10t_30_soffqbcka01	25.00			25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12252.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12258.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12261.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12266.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12269.xdti_28hc_10t_30_soffqbcka01	50.00			50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12273.xdti_28hc_10t_30_soffqbcka01	37.50			37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12288.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12297.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12309.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12328.xdti_28hc_10t_30_soffqbcka01	12.50			12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12330.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12332.xdti_28hc_10t_30_soffqbcka01	45.83			45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12333.xdti_28hc_10t_30_soffqbcka01	12.50			12.50


Ports	10	6	60.00
Port Bits	20	12	60.00
Port Bits 0->1	10	6	60.00
Port Bits 1->0	10	6	60.00

Name	Toggle	Toggle 1->0	Toggle 0->1	Direction
VDD	No	No	No	INPUT
VSS	No	No	No	INPUT
Q	Yes	Yes	Yes	OUTPUT
SO	Yes	Yes	Yes	OUTPUT
CK	Yes	Yes	Yes	INPUT
D	Yes	Yes	Yes	INPUT
SD	Yes	Yes	Yes	INPUT
SE	No	No	No	INPUT
RN	Yes	Yes	Yes	INPUT
notifier	No	No	No	INPUT

Name	Toggle	Toggle 1->0	Toggle 0->1
CE	No	No	No
SN	No	No	No

	Total	Covered	Percent
Totals	12	6	50.00
Total Bits	24	12	50.00
Total Bits 0->1	12	6	50.00
Total Bits 1->0	12	6	50.00


Signals	2	0	0.00
Signal Bits	4	0	0.00
Signal Bits 0->1	2	0	0.00
Signal Bits 1->0	2	0	0.00